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general description the MAX1515 constant-off-time, pulse-width-modulated (pwm) source/sink step-down dc-dc converter is opti- mized for use in low-voltage active-termination power rails or chipset power supplies in notebook and sub- notebook computers. this device features dual internal n-channel mosfet power switches for high efficiency and reduced component count. external schottky diodes are not required. an integrated boost switch eliminates the need for an external boost diode. the internal 40m nmos power switches easily source and sink continuous load currents up to 3a. the MAX1515 produces an adjustable output from +0.5v to +2.7v and achieves efficiencies as high as 95%. the MAX1515 can be configured as a ddr regulator, producing an output that is exactly half the memory supply rail. the input of the power stage can be taken from the memory supply rail itself, resulting in an effi- cient power supply that returns the energy to the rail from which it was sourced. the MAX1515 includes a reference buffer that provides ?ma of drive current. the MAX1515 uses a unique current-mode, constant- off-time, pwm control scheme. a selectable pulse-skip- ping mode maintains high efficiency during light-load operation, yet still sources and sinks current on demand. the MAX1515 can also be operated in fixed- pwm mode for low output ripple. the programmable constant-off-time architecture sets switching frequen- cies up to 1mhz, which allows the user to optimize per- formance trade-offs between efficiency, output switching noise, component size, and cost. the MAX1515 features an adjustable soft-start to limit surge currents during startup and a low-power shutdown mode to disconnect the input from the output and reduce supply current below 1a. the MAX1515 is available in a 24-pin thin qfn package with an exposed backside pad. applications notebook ddr memory termination active-termination buses chipset/graphics processor supplies features ? dual 40m internal n-channel mosfets ? integrated boost switch ? +1.3v to +3.6v input voltage range ? 1% v out accuracy over line and load ? 1mhz maximum switching frequency ? ddr termination regulator (ddr mode) tracking output voltage source/sink pulse skipping ?ma reference buffer ? output voltage (non-ddr mode) +2.5v, +1.8v, or +1.5v pin selectable +0.5v to +2.7v adjustable ? 1.1v ?.75% reference output ? adjustable soft-start inrush current limiting ? < 1? (typ) shutdown supply current ? < 800? (max) operating supply current ? selectable pulse-skipping operation at light loads ? positive and negative current limit ? power-good window comparator ? output short-circuit protection MAX1515 low-voltage, internal switch, step-down/ddr regulator ________________________________________________________________ maxim integrated products 1 ordering information MAX1515 lx gnd v cc fb comp pgnd in refout pgood v bias (3.0v to 3.6v) v in (1.3v to 3.6v) v out = v tt v refout = v ttr v ddq (2.5v or 1.8v) mode fbsel1 bst v dd shdn skip fbsel0 ss refin ref toff minimal operating circuit 19-3507; rev 1; 3/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package pkg code MAX1515etg -40? to +85? 24 thin qfn 4mm x 4mm t2444-4 MAX1515etg+ -40? to +85? 24 thin qfn 4mm x 4mm t2444-4 pin configuration appears at end of data sheet. + denotes lead-free package.
MAX1515 low-voltage, internal switch, step-down/ddr regulator 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v in = +3.3v, v cc = v dd = shdn = mode = +3.3v, v refin = v ref , skip = gnd, t a = 0? to +85? , unless oth- erwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , v dd , lx, shdn to gnd ...................................-0.3v to +4v mode, ic to gnd ....................................................-0.3v to +4v comp, fb, ref, refin, refout, pgood to gnd.........................................................-0.3v to (v cc + 0.3v) fbsel0, fbsel1, toff, skip , ss to gnd....-0.3v to (v cc + 0.3v) v dd to v cc ...........................................................-0.3v to + 0.3v in to v dd ....................................................-0.3v to (v dd + 0.3v) pgnd to gnd ...................................................... -0.3v to +0.3v lx to bst................................................................. -4v to +0.3v bst to gnd .......................................................... -0.3v to +8.0v lx current (note 1).............................................................?.7a ref short circuit to gnd ...........................................continuous refout short circuit to gnd....................................continuous continuous power dissipation (t a = +70?) 24-pin thin qfn (derate 20.8mw/? above +70?; part mounted on 1in 2 of 1oz copper)........................1667mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units pwm controller v in 1.3 3.6 input voltage range v cc , v dd 3.0 3.6 v output adjust range v out v in 0.5 2.7 v t a = +25? to +85? -3 0 +3 v fb - v refin v in = +3.3v, i load = 0, mode = v cc t a = 0? to +85? -4 0 +4 mv t a = +25? to +85? 2.463 2.5 2.537 fbsel0 = v cc , fbsel1 = v cc , refin = ref t a = 0? to +85? 2.450 2.5 2.550 t a = +25? to +85? 1.782 1.800 1.827 fbsel0 = v cc , fbsel1 = gnd, refin = ref t a = 0? to +85? 1.773 1.800 1.836 t a = +25? to +85? 1.477 1.500 1.523 fbsel0=gnd fbsel1=v cc refin=ref t a = 0? to +85? 1.470 1.500 1.530 t a = +25? to +85? 0.492 0.500 0.508 feedback voltage accuracy v fb v in = +3.3v, i load = 0, mode = low fbsel0=gnd fbsel1=gnd refin=0.5v t a = 0? to +85? 0.490 0.500 0.510 v feedback load-regulation error v in = +1.3v to +3.6v, i load = 0 to 3a, skip = v cc 0.1 % note 1: lx has clamp diodes to pgnd and in. if continuous current is applied through these diodes, thermal limits must be observed.
MAX1515 low-voltage, internal switch, step-down/ddr regulator _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v in = +3.3v, v cc = v dd = shdn = mode = +3.3v, v refin = v ref , skip = gnd, t a = 0? to +85? , unless oth- erwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units sink-mode detect threshold v fb - v refin mode = v cc , v refin = +0.5v to +1.5v +18 +32 mv source-mode detect threshold v fb - v refin mode = v cc , v refin = +0.5v to +1.5v -32 -18 mv mosfet on-resistance r nmos v cc = v dd = v in = +3.3v, i load = 0.5a 0.04 0.10 switching frequency f sw (note 2) 1 mhz maximum output current i out ( rms ) (note 3) 3.3 a i limit_p v in = +3.3v, mode = gnd or v cc , positive or sourcing mode 3.60 4.2 4.85 current-limit threshold i limit_n mode = v cc , negative or sinking mode -3.0 a pulse-skipping current threshold i skip_p v in = +3.3v, mode = gnd or v cc , positive or sourcing mode 0.5 0.8 1.1 a i zx_p v in = +3.3v, mode = gnd or v cc , positive or sourcing mode 200 zero cross current threshold i zx_n mode = v cc , negative or sinking mode -350 ma fb input bias current fb = 1.01 x v target (note 4) -50 +50 na r toff = 33.2k 0.270 0.34 0.405 r toff = 110k 0.85 1.00 1.15 off-time t off v fb > 0.3 x v target (note 4) r toff = 499k 3.8 4.5 5.2 ? extended off-time t off ( ext ) v fb < 0.3 x v target (notes 2, 4) 4 x t off ? minimum on-time t on ( min ) (note 2) 180 ns maximum on-time t on ( max ) 511 s ss source current i ss ( src ) 3.50 5.25 6.75 ? ss sink current i ss ( snk ) 100 ? mode = gnd, fbsel0 = gnd, fbsel1 = gnd, v fb = 1.01 x v target 450 800 no-load supply current i cc + i dd + i in v in = 3.3v (not switching) (note 4) mode = v cc , v fb = v target 700 1200 ? i cc + i dd + i in shdn = mode = gnd, lx = 0v or 3.3v 0.2 20 i in shdn = mode = gnd, lx = 0v 0.2 20 shutdown supply currents i lx shdn = mode = gnd, lx = 3.3v 0.1 20 ?
MAX1515 low-voltage, internal switch, step-down/ddr regulator 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = +3.3v, v cc = v dd = shdn = mode = +3.3v, v refin = v ref , skip = gnd, t a = 0? to +85? , unless oth- erwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units reference t a = +25? to +85? 1.0923 1.100 1.1077 reference voltage v ref v cc = +3.0v to +3.6v t a = 0? to +85? 1.0907 1.100 1.1094 v reference load regulation i ref = -1? to +50? 10 mv refin input voltage range v refin v cc = +3.0v to +3.6v 0.5 1.5 v v refin = +0.5v to +1.5v i refout = -1ma to +1ma -10 +10 refout output accuracy v refin - v refout v refin = +0.5v to +1.5v i refout = -5ma to +5ma -20 +20 mv refin input bias current i refin v refin = 1.1v -50 +50 na fault detection thermal shutdown t shdn rising, hysteresis = 15? +165 ? undervoltage-lockout threshold v cc ( uvlo ) v cc rising, 2% falling-edge hysteresis 2.5 2.7 2.9 v pgood trip threshold (lower) no load, falling edge, hysteresis = 1% -13 -10 -7 % pgood trip threshold (upper) no load, rising edge, hysteresis = 1% +7 +10 +13 % pgood propagation delay t pgood fb forced 2% beyond pgood trip threshold 10 ? pgood output low voltage i sink = 1ma 0.1 v pgood leakage current condition h i g h state, for ced to 3.6v ; v c c = v d d = 3.6v 1a inputs and outputs logic input high voltage skip , shdn , mode, fbsel0, fbsel1 2.0 v logic input low voltage skip , shdn , mode, fbsel0, fbsel1 0.8 v logic input current skip , shdn , mode, fbsel0, fbsel1 -0.5 +0.5 ?
MAX1515 low-voltage, internal switch, step-down/ddr regulator _______________________________________________________________________________________ 5 electrical characteristics (circuit of figure 1, v in = +3.3v, v cc = v dd = shdn = mode = +3.3v, v refin = v ref , skip = gnd, t a = -40? to +85? , unless otherwise noted. note 5) parameter symbol conditions min typ max units pwm controller v in 1.3 3.6 input voltage range v cc , v dd 3.0 3.6 v output adjust range v out v in 0.5 v cc v v fb - v refin v in = +3.3v, i load = 0, mode = v cc -5 +5 mv fbsel0 = v cc , fbsel1 = v cc , refin = ref 2.438 2.562 fbsel0 = v cc , fbsel1 = gnd, refin = ref 1.755 1.845 fbsel0 = gnd, fbsel1 = v cc , refin = ref 1.463 1.538 feedback voltage accuracy v fb v in = +3.3v, i load = 0, mode = low fbsel0 = gnd, fbsel1 = gnd, refin = 0.5v 0.487 0.513 v sink-mode detect threshold v fb - v refin mode = v cc , v refin = +0.5v to +1.5v +15 +35 mv source-mode detect threshold v fb - v refin mode = v cc , v refin = +0.5v to +1.5v -35 -15 mv nfet on-resistance r nmos v cc = v dd = v in = +3.3v, i load = 0.5a 0.10 switching frequency f sw (note 2) 1 mhz current-limit threshold i limit_p v in = +3.3v, mode = gnd or v cc , positive or sourcing mode 3.35 5.05 a pulse-skipping current threshold i skip_p v in = +3.3v, mode = gnd or v cc , positive or sourcing mode 0.4 1.2 a r toff = 33.2k 0.250 0.425 r toff = 110k 0.8 1.2 off-time t off v fb > 0.3 x v target (note 4) r toff = 499k 3.8 5.2 ? maximum on-time t on ( max ) 5s ss source current i ss ( src ) 37a ss sink current i ss ( snk ) 100 ?
MAX1515 low-voltage, internal switch, step-down/ddr regulator 6 _______________________________________________________________________________________ note 2: guaranteed by design. not production tested. note 3: not tested; guaranteed by layout. maximum output current may be limited by thermal capability to a lower value. note 4: v target is the set output voltage determined by v refin , fbsel0, and fbsel1. note 5: specifications to -40? are guaranteed by design, not production tested. electrical characteristics (continued) (circuit of figure 1, v in = +3.3v, v cc = v dd = shdn = mode = +3.3v, v refin = v ref , skip = gnd, t a = -40? to +85? , unless otherwise noted. note 5) parameter symbol conditions min typ max units mode = gnd, fbsel0 = fbsel1 = gnd, v fb = 1.01 x v target 900 no-load supply current i cc + i dd + i in v in = 3.3v (note 4) mode = v cc v fb = v target 1300 ? i cc + i dd + i in shdn = mode = gnd, lx = 0v or 3.3v 20 i in shdn = mode = gnd, lx = 0v 20 shutdown supply currents i lx shdn = mode = gnd, lx = 3.3v 20 ? reference reference voltage v ref v cc = +3.0v to +3.6v 1.086 1.114 v reference load regulation i ref = -1? to +50? 12 mv refin input voltage range v refin v c c = + 3.0v to + 3.6v , v c c > v re f in + 1.35v 0.5 1.5 v v refin = +0.5v to +1.5v i refout = -1ma to +1ma -15 +15 refout output accuracy v refin - v refout v refin = +0.5v to +1.5v i refout = -5ma to +5ma -25 +25 mv fault detection undervoltage-lockout threshold v cc ( uvlo ) v cc rising, 2% falling-edge hysteresis 2.40 2.95 v pgood trip threshold (lower) no load, falling edge, hysteresis = 1% -13 -7 % pgood trip threshold (upper) no load, rising edge, hysteresis = 1% +7 +13 % inputs and outputs logic input high voltage skip , shdn , mode, fbsel0, fbsel1 2.0 v logic input low voltage skip , shdn , mode, fbsel0, fbsel1 0.8 v
MAX1515 low-voltage, internal switch, step-down/ddr regulator _______________________________________________________________________________________ 7 1.25v output efficiency vs. load current MAX1515 toc01 load current (a) efficiency (%) 1 0.1 0.01 10 20 30 40 50 60 70 80 90 100 0 0.001 10 sink, skip source, pwm sink, pwm source, skip v in = 2.5v v out = 1.25v r toff = 110k 1.25v output efficiency vs. load current MAX1515 toc02 load current (a) efficiency (%) 1 0.1 0.01 10 20 30 40 50 60 70 80 90 100 0 0.001 10 sink, skip source, pwm sink, pwm source, skip v in = 2.5v v out = 1.25v r toff = 220k 1.25v output voltage vs. load current MAX1515 toc03 load current (a) output voltage (v) 3 2 -2 -1 0 1 1.246 1.250 1.254 1.258 1.242 -3 4 sink, skip source, pwm sink, pwm source, skip v in = 2.5v v out = 1.25v r toff = 110k 0.9v output efficiency vs. load current MAX1515 toc04 load current (a) efficiency (%) 1 0.1 0.01 10 20 30 40 50 60 70 80 90 100 0 0.001 10 sink, skip source, pwm sink, pwm source, skip v in = 1.8v v out = 0.9v r toff = 110k 0.9v output efficiency vs. load current MAX1515 toc05 load current (a) efficiency (%) 1 0.1 0.01 10 20 30 40 50 60 70 80 90 100 0 0.001 10 sink, skip source, pwm sink, pwm source, skip v in = 1.8v v out = 0.9v r toff = 220k 0.9v output voltage vs. load current MAX1515 toc06 load current (a) output voltage (v) 3 2 -2 -1 0 1 0.896 0.900 0.904 0.908 0.892 -3 4 sink, skip source, pwm sink, pwm source, skip v in = 1.8v v out = 0.9v r toff = 110k switching frequency vs. load current MAX1515 toc07 load current (a) switching frequency (khz) 3 2 1 0 -1 -2 100 200 300 400 500 600 0 -3 4 pwm mode skip mode v in = 2.5v v out = 1.25v typical operating characteristics (MAX1515 circuit of figure 1, v in = 2.5v, v dd = v cc = shdn = mode = 3.3v, t a = +25?, unless otherwise noted.)
MAX1515 low-voltage, internal switch, step-down/ddr regulator 8 _______________________________________________________________________________________ typical operating characteristics (continued) (MAX1515 circuit of figure 1, v in = 2.5v, v dd = v cc = shdn = mode = 3.3v, t a = +25?, unless otherwise noted.) ref voltage vs. ref load current MAX1515 toc08 ref load current ( a) ref voltage error (v) 80 60 20 40 1.098 1.100 1.102 1.104 1.096 0100 refout voltage regulation vs. load current MAX1515 toc09 refout load current (ma) refout voltage (v) 10 5 0 -5 -10 1.240 1.245 1.250 1.255 1.260 1.265 1.235 -15 15 toff time vs. toff resistor MAX1515 toc10 toff resistor (k ) toff ( s) 400 300 200 100 1 2 3 4 5 0 0500 peak current limit vs. ss voltage MAX1515 toc11 ss voltage (v) peak current limit (a) 1.6 1.4 1.2 1 2 3 4 5 0 1.0 1.8 v in = 2.5v v out = 1.25v r toff = 110k startup and shutdown waveform (heavy load) MAX1515 toc12 500 s/div 3.3v a b c d e 0 0 0 1a 0 1.25v 0 a: pgood, 5v/div b: ss, 2v/div c: shdn, 5v/div d: inductor current, 1a/div e: output voltage, 1v/div skip = gnd, r load = 10
MAX1515 low-voltage, internal switch, step-down/ddr regulator _______________________________________________________________________________________ 9 typical operating characteristics (continued) (MAX1515 circuit of figure 1, v in = 2.5v, v dd = v cc = shdn = mode = 3.3v, t a = +25?, unless otherwise noted.) startup and shutdown waveform (light load) MAX1515 toc13 1ms/div 3.3v a b c d e 0 0 0 1a 0 1.25v 0 a: pgood, 5v/div b: ss, 2v/div c: shdn, 5v/div d: inductor current, 1a/div e: output voltage, 1v/div skip = gnd, r load = 100 ddr-mode load transient MAX1515 toc14 20 s/div 2.5v a b c d 0 0 2a 0 2a 1.25v a: lx, 2v/div b: load control, 5v/div c: inductor current, 2a/div d: output voltage, 50mv/div skip = gnd ddr-mode load transient MAX1515 toc15 20 s/div 2.5v a b c d 0 0 2a 0 -2a 1.25v a: lx, 2v/div b: load control, 5v/div c: inductor current, 2a/div d: output voltage, 50mv/div skip = gnd ddr-mode load transient MAX1515 toc16 20 s/div 2.5v a b c d 0 0 2a 0 -2a 1.25v a: lx, 2v/div b: load control, 5v/div c: inductor current, 2a/div d: output voltage, 50mv/div skip = gnd
MAX1515 low-voltage, internal switch, step-down/ddr regulator 10 ______________________________________________________________________________________ typical operating characteristics (continued) (MAX1515 circuit of figure 1, v in = 2.5v, v dd = v cc = shdn = mode = 3.3v, t a = +25?, unless otherwise noted.) ddr-mode load transient MAX1515 toc17 20 s/div 2.5v a b c d 0 0 2a 0 -2a 1.25v a: lx, 2v/div b: load control, 5v/div c: inductor current, 2a/div d: output voltage, 50mv/div skip = gnd ddr-mode load transient MAX1515 toc18 20 s/div 2.5v a b c d 0 0 2a 0 -2a 1.25v a: lx, 2v/div b: load control, 5v/div c: inductor current, 2a/div d: output voltage, 50mv/div skip = gnd refin transition MAX1515 toc19 50 s/div 3.3v a b c d 0 1.5v 1.0v 1.5v 1.0v 2a 0a -2a a: pgood, 5v/div b: refin, 0.5v/div c: output voltage, 0.5v/div d: inductor current, 2a/div skip = gnd refout load transient MAX1515 toc20 10 s/div a b +10ma -10ma 1.25v 1.26v 1.24v a: refout load, 20ma/div b: refout voltage, 10mv/div
MAX1515 low-voltage, internal switch, step-down/ddr regulator ______________________________________________________________________________________ 11 pin description pin name function 1, 2 pgnd power ground. internal connection to the source of the internal synchronous-rectifier switch. connect both pgnd pins together. 3 ic internally connected pin. connect to pgnd. 4v dd supply input for the low-side gate drive and refout buffer. connect to the system supply voltage, +3.0v to +3.6v. bypass to pgnd with a 1? (min) ceramic capacitor. v dd supplies power to the drivers and the refout buffer. 5 refout refin buffered output. refout provides a buffered output voltage of refin when mode = v cc . bypass to gnd with a 0.47? ceramic capacitor. refout is disabled when mode = gnd. 6 ss soft-start. connect a capacitor from ss to gnd to limit the inrush current during startup. 7 pgood power-good open-drain output. pgood is low when the output voltage is more than 10% above or below the normal regulation point. pgood is high impedance when the output is in regulation. pgood is low in shutdown. 8 toff off-time select input. connect a resistor from toff to gnd to adjust the off-time. 9fb feedback input. in ddr mode (mode = v cc ), fb regulates to the voltage at refin. in non-ddr mode (mode = gnd), connect directly to the output for preset voltage operation or to a resistive voltage-divider for adjustable-mode operation. 10 comp integrator compensation. connect a 470pf capacitor from comp to v cc for integrator compensation. 11 v cc analog supply input. connect to the system supply voltage, +3.0v to +3.6v, with a series 10 resistor. bypass to gnd with a 1? (min) ceramic capacitor. 12 gnd analog ground. connect exposed backside pad to gnd. 13 ref +1.1v reference voltage output. bypass to gnd with a 1.0? bypass capacitor. can supply 50? for external loads. reference turns off in shutdown. 14 refin external reference input. in ddr mode (mode = v cc ), refin sets the voltage that fb regulates to. in non-ddr mode (mode = gnd), connect refin to ref. 15 shdn shutdown control. low disables the switching regulator. shdn and mode select the operational mode of the MAX1515. shdn mode description low low step-down regulator and refout off low high step-down regulator off, refout active high low step-down regulator on, non-ddr mode, refout off high high step-down regulator on, ddr mode, refout active 16 mode mode-select pin. mode sets the regulator into ddr mode or non-ddr operation mode, and controls the refout buffer. when mode = v cc , MAX1515 is set in ddr mode and refout is active. when mode = gnd, MAX1515 is set in non-ddr mode and refout is disabled. see the modes of operation (mode) section. 17 fbsel0 used with fbsel1 to set the output voltage of the step-down regulator when mode = gnd. connect to gnd if mode = v cc .
MAX1515 low-voltage, internal switch, step-down/ddr regulator 12 ______________________________________________________________________________________ standard application circuit the MAX1515 standard application circuit (figure 1) generates a tracking output voltage and a reference buffer output required for ddr termination regulators. see table 1 for component selections. table 2 lists the component manufacturers. detailed description the MAX1515 synchronous, current-mode, constant off-time, pwm dc-dc converter steps down an input voltage (v in ) from +1.3v to +3.6v to an output voltage from +0.5v to +2.7v. the MAX1515 output delivers up to 3a of continuous current. internal 40m nmos power switches improve efficiency, reduce component count, and eliminate the need for a boost diode or any external schottky diodes (figure 2). pin description (continued) pin name function 18 fbsel1 used with fbsel0 to set the output voltage of the step-down regulator when mode = gnd. connect to gnd if mode = v cc . 19 skip pulse-skipping control input. connect to v cc for low-noise, forced-pwm mode. connect to gnd to enable automatic pulse-skipping operation. 20 bst boost flying-capacitor connection. connect an external 0.01? capacitor as shown in the standard application circuit (figure 1). 21, 22 lx inductor switched node. lx is the connection for the source of the high-side nmos power switch and drain of the low-side nmos synchronous-rectifier switch. connect both lx pins together. 23, 24 in power input. supply voltage input for the switching regulator. connect to a +1.3v to +3.6v supply voltage. connect both in pins together. table 1. component selection for standard applications component ?a at 1.25v out ddr mode (mode = v cc ) ?a at 0.9v out ddr mode (mode = v cc ) input voltage (v in ) 2.3v to 2.7v 1.6v to 2.0v output voltage (v out ) 1.25v 0.9v c in , input capacitor 33?, 6.3v, ceramic tdk c3225xr0j336v 33?, 6.3v, ceramic tdk c3225xr0j336v switching frequency (f sw ) 250khz 500khz 250khz 500khz l, inductor 2.5?, 4.5a, sumida cdrh8d28-2r5 1.2?, 6.8a, sumida cdr7d28mn-1r2 2.5?, 4.5a, sumida cdrh8d28-2r5 1.2?, 6.8a, sumida cdr7d28mn-1r2 c out , output capacitor 330?, 18m sanyo 2r5tpe330mi poscap 220?, 18m sanyo 2r5tpe220mi poscap 330?, 18m sanyo 2r5tpe330mi poscap 220?, 18m sanyo 2r5tpe220mi poscap r toff 221k , 1% 110k , 1% 221k , 1% 110k , 1% table 2. component suppliers supplier website coilcraft www.coilcraft.com coiltronics www.coiltronics.com kemet www.kemet.com panasonic www.panasonic.com sanyo www.sanyo.com sumida www.sumida.com taiyo yuden www.t-yuden.com tdk www.component.tdk.com toko www.tokoam.com
MAX1515 low-voltage, internal switch, step-down/ddr regulator ______________________________________________________________________________________ 13 MAX1515 lx gnd v cc fb comp pgnd in refout pgood v bias (3.0v to 3.6v) v cc (ddr mode) v in (1.3v to 3.6v) v out = v tt = v ddc / 2 v refout = v ttr v ddq (2.5v or 1.8v) mode fbsel1 bst v dd shdn skip fbsel0 ss refin ref toff r1 10 r2 100k r toff 110k r ss (optional) c ss 0.01 f c bst 0.01 f pwm mode skip mode on off r3 10k 1% r4 10k 1% see table 1 for component specifications c vdd 1 f c in 33 f c out 220 f c refout 0.47 f l 1.2 h c vcc 1 f c refin 0.01 f c comp 470pf c ref 1 f err MAX1515 lx snk/src threshold src snk in pgnd fb fb gain sink/ source logic ss soft- start pwm logic comp toff timer current sense zx(+) current sense (+/-) zx(-) gnd bst shdn mode fbsel0 fbsel1 fbsel decode skip v dd l-side driver h-side driver pgood pgood logic v dd ref buf refin refout ref ref 1.1v v cc mode g m figure 1. standard application circuit figure 2. functional diagram
MAX1515 low-voltage, internal switch, step-down/ddr regulator 14 ______________________________________________________________________________________ +3.3v bias supply (v cc and v dd ) the MAX1515 requires a 3.3v bias supply for its inter- nal circuitry. typically, this 3.3v bias supply is the note- book? 95%-efficient, 3.3v system supply. the 3.3v bias supply must provide v cc (pwm controller) and v dd (gate-drive and reference buffer power), so the maximum current drawn is: i bias = i cc + i refout + f sw (q g(low) + q g(high) ) where i cc is 450? (typ), f sw is the switching frequen- cy, and q g(low) and q g(high) are the internal mos- fet total gate charge of approximately 1nc. the input supply (v in ) and 3.3v bias inputs (v cc and v dd ) can be connected together if the input source is a fixed 3.0v to 3.6v supply. if the 3.3v bias supply pow- ers up prior to the input supply, the enable signal ( shdn going from low to high) must be delayed until the input voltage is present to ensure startup. current limit the MAX1515 provides peak current limiting to protect the mosfets during source/sink overload and short circuit. during source mode the controller switches the high-side mosfet off when the inductor current exceeds 4.2a. use the following equation to calculate the maximum source current: where i source_max is the maximum source current, i limit_p is the source inductor current limit (4.2a typ), and t off is the fixed off-time. for typical operating con- ditions and component selection, this results in a maxi- mum source current of 3.7a. in sink mode, the MAX1515 does not issue an off-time until the inductor current is above -3.2a. use the follow- ing equation to calculate the maximum sink current: where i sink_max is the maximum sink current, i limit_n is the sink inductor current limit (-3.0a typ), t dly is the current-limit propagation delay of approximately 500ns, and t off is the fixed off-time. for typical operating con- ditions and component selection, this results in a maxi- mum sink current of -2.5a. soft-start current limit soft-start allows a gradual increase of the internal cur- rent limit to reduce input surge currents at startup and at exit from shutdown. a timing capacitor, c ss , placed from ss to gnd sets the rate at which the internal cur- rent limit is changed. upon power-up, when the device comes out of undervoltage lockout (2.6v typ) or after the shdn pin is pulled high, a 5a (typ) constant-current source charges the soft-start capacitor and the voltage on ss increases. when the voltage on ss is less than approximately 0.7v, the current limit is set to zero. as the voltage increases from 0.7v to approximately 1.8v, the current limit is adjusted from 0 to the current-limit threshold (see the electrical characteristics ). the volt- age across the soft-start capacitor changes with time according to the equation: where i ss(src) is the soft-start source current from the electrical characteristics . the time when full current limit is available is given by: the soft-start current limit varies with the voltage on the soft-start pin, ss, according to the equation: where i limit_p is the positive current threshold from the electrical characteristics . the constant-current source stops charging once the voltage across the soft-start capacitor reaches 1.8v (figure 3). adjustable positive current limit the MAX1515 has internal current-limit circuitry that limits the maximum current through the nmos to 4.2a. for applications that require a lower current limit, the maximum current limit can be reduced by placing a resistor (r ss ) from ss to gnd. the time constant for the soft-start current limit is r ss x c ss . where i limit is the desired reduced current limit, and i limit_p and i ss(src) are taken from the electrical characteristics . r vi i vi ss ref limit limit p ss src = + ? ? ? ? ? ? . / _ () 07 ssi vv v i limit ss ref limit p = ? 07 . _ t cv i ss ss src = 18 . () v it c ss ss src ss = () ii vt v v t l sink max limit n out off in out dly _ _ =+ () ?? 2 2 ii vt l source max limit p out off __ = ? 2
MAX1515 low-voltage, internal switch, step-down/ddr regulator ______________________________________________________________________________________ 15 short-circuit/overload protection the MAX1515 can sustain a constant short circuit or overload. under a source-mode short-circuit or over- load condition, when v fb < 0.3 x v target , the MAX1515 uses an extended off-time to control the cur- rent. operation during a short circuit or overload is sim- ilar to forced-pwm mode except the off-time is 4 x t off. at the end of each off-time, the high-side nmos switch turns on and remains on until the output is in regulation or the current through the switch increases to the maxi- mum current limit. when the high-side nmos switch turns off, it remains off for four times the programmed off-time (t off ), and the low-side nmos synchronous switch turns on. since either nmos switch is always on, the inductor current is continuous. the rms inductor current during a short circuit remains below the maxi- mum current-limit threshold. the MAX1515 operates using the extended off-time until the short circuit or overload is removed and v fb > 0.3 x v target . prolonged short circuit or overload can result in thermal shutdown. summing comparator three signals are added together at the input of the summing comparator (figure 2): an output-voltage error signal relative to the reference voltage, an inte- grated output-voltage error-correction signal, and the sensed high-side nmos switch current. the integrated error signal is provided by a transconductance amplifi- er with an external capacitor at comp. this integrator provides high dc accuracy without the need for a high- gain amplifier. connecting a capacitor at comp modi- fies the overall loop response (see the integrator amplifier section). integrator amplifier the MAX1515 includes an internal transconductance amplifier that improves the output dc accuracy. a capacitor, c comp , from comp to v cc compensates the transconductance amplifier. for stability, choose c comp = 470pf. modes of operation (mode) use mode to configure the MAX1515 for ddr mode (mode = v cc ) or non-ddr mode (mode = gnd). in ddr mode, the MAX1515 can sink current even while skip is low (see the pulse skipping (source mode) and pulse skipping (sink mode) sections). also, ddr mode enables the refout buffer, providing a buffered out- put of the refin voltage. in non-ddr mode, the MAX1515 can only source current when skip is low. the refout buffer is also disabled in non-ddr mode. light-load operation ( skip ) the MAX1515 includes a pulse-skipping mode that reduces current consumption during light loads. to con- figure the MAX1515 for pulse-skipping mode, connect skip to gnd. forced-pwm mode keeps the switching frequency relatively constant and is desirable in appli- cations that must always keep the frequency of con- ducted and radiated emissions in a narrow band. visit maxim? website (www.maxim-ic.com) for more informa- tion on how to control electromagnetic interference (emi). pulse-skipping mode has a dynamic switching frequency under light loads and is desirable in applica- tions that require high efficiency at light loads. forced-pwm mode connect skip to v cc to force the MAX1515 to operate in low-noise, constant-off-time pwm mode. constant off-time pwm architecture provides a relatively constant switching frequency (see the frequency variation with output current section). a single resistor (r toff ) sets the high-side nmos power-switch off-time that results in a switching frequency up to 1mhz, allowing perfor- mance trade-offs in efficiency, switching noise, compo- nent size, and cost. forced-pwm mode regulates the output voltage by increasing the high-side nmos switch on-time to increase the amount of energy transferred to the load per cycle. at the end of each off-time, the high-side nmos switch turns on and remains on until the output is in regulation or the current through the switch reaches the 4.2a current limit. when the high-side nmos switch turns off, it remains off for the programmed off-time (t off ), and the low-side nmos synchronous switch turns on. the low-side nmos switch remains on until the end of t off . since either nmos switch is always on in pwm mode, the inductor current is continuous. 1.8v 0.7v i limit_p v ss (v) i limit (a) shdn figure 3. soft-start current limit
MAX1515 low-voltage, internal switch, step-down/ddr regulator 16 ______________________________________________________________________________________ pulse skipping (source mode) connect skip to gnd to allow the MAX1515 to auto- matically switch between high-efficiency pulse-skipping mode under light loads and pwm mode under heavy loads. the transition from pwm mode to pulse-skipping mode occurs when the load current is half the pulse- skipping mode current threshold (800ma typ). in pulse-skipping mode, the switching frequency is reduced to increase efficiency. the inductor current is discontinuous in this mode, and the MAX1515 only initi- ates an lx switching cycle when v fb < v refin . when v fb falls below v refin , the high-side nmos switch turns on and remains on until output is in regulation and the current through the switch increases to the positive pulse-skipping-mode current threshold (i skip_p ) of 800ma. when the high-side nmos switch turns off, the low-side nmos synchronous switch turns on and remains on until the current through the switch decreas- es to the zero-cross-current threshold of 200ma. pulse skipping (sink mode) when pulse-skipping operation is selected ( skip = gnd) while in ddr mode (mode = v cc ), the MAX1515? source/sink controller switches operating modes when the output voltage crosses either hys- teretic sink/source thresholds (v refin ?5mv). in pulse-skipping source mode, the MAX1515 regulates the valley of the output ripple voltage (see the pulse skipping (source mode) section). when the output volt- age rises above the sink-mode threshold, the MAX1515 enters sink mode. the MAX1515 begins each sink- mode cycle by turning on the low-side nmos. the low- side nmos remains on until the off-time (t off ). after the low-side nmos turns off, the high-side nmos turns on and remains on until the current through the switch reaches the zero-cross-current threshold of -350ma. as long as the output voltage remains below the feedback threshold, the controller remains in the high-impedance state. under light-load conditions, this allows the sink- mode controller to automatically skip pulses. under heavy-load conditions, the output voltage remains above the feedback threshold, forcing the sink-mode controller to emulate typical forced-pwm operation. the pulse-skipping current threshold allows the sink- mode control scheme to automatically switch between pulse-skipping pfm and nonskipping pwm operation. this mechanism forces the boundary between continu- ous and discontinuous inductor-current operation to be half the negative pulse-skipping current threshold. output voltage in non-ddr mode in non-ddr mode (mode = gnd and v refin = v ref ), the output of the MAX1515 is selectable between one of three preset output voltages: 2.5v, 1.8v, and 1.5v. for a preset output voltage, connect fb to the output voltage and connect fbsel0 and fbsel1 as indicated in table 4. for an adjustable output voltage, connect fbsel0 and fbsel1 to gnd and connect refin to a table 3. modes of operation shdn mode pin skip refout buffer step-down regulator mode step-down regulator current low low x off, high-z off off low high x on off off high low low off, high-z on, non-ddr mode. fb regulates to preset voltage or 0.5v. source only. pulse-skipping mode. high low high off, high-z on, non-ddr mode. fb regulates to preset voltage or 0.5v. source/sink. forced-pwm mode. high high low on on, ddr mode. fb regulates to refin. source/sink. pulse-skipping mode. high high high on on, ddr mode. fb regulates to refin. source/sink. forced-pwm mode. table 4. output-voltage programming fbsel0 fbsel1 output voltage gnd gnd adjustable v fb = v refin gnd v cc 1.5v v cc gnd 1.8v v cc v cc 2.5v x = don? care.
MAX1515 low-voltage, internal switch, step-down/ddr regulator ______________________________________________________________________________________ 17 resistive divider between ref and ground (figure 5). regulation is maintained for adjustable output voltages when v fb = v refin . use 100k for r b . r a is given by the equation: where v ref = 1.1v. the preset output voltages use an internally trimmed resistor-divider network that sets the output voltage to the correct level when refin is connected to ref. connecting refin to other voltage levels while using the preset voltage modes results in a ratiometrically scaled output voltage. output voltage in ddr mode in ddr mode (mode = v cc ), the MAX1515 regulates fb to the voltage set at refin. for ddr applications, the termination supply must track to exactly half the memory supply voltage. figure 1 shows the MAX1515 configured for ddr applications. reference buffer (refout) a unity-gain amplifier provides a buffered output for the reference input (v refin ) when mode = v cc . this transconductance amplifier must be compensated with a 0.47? or greater ceramic capacitor. larger capaci- tor values decrease the amplifier? bandwidth, thereby increasing the response time to dynamic input-voltage changes. the buffer allows this dynamic reference to remain within ?0mv of the input voltage (v refin ) even when loaded with ?ma. the input voltage range of the amplifier is 0.5v to 1.5v. the reference buffer shuts down when mode = gnd. power-good output (pgood) pgood is the open-drain output for a window compara- tor that continuously monitors the output. pgood is actively held low in shutdown and during soft-start. after soft-start terminates, pgood becomes high impedance as long as the respective output voltage is within ?0% of the nominal regulation voltage. when the output volt- age drops 10% below or rises 10% above the nominal regulation voltage, the MAX1515 pulls the power-good output (pgood) low by turning on the mosfet (figure 2). for logic-level output voltages, connect an external pullup resistor between pgood and v cc . a 100k resistor works well in most applications. thermal shutdown the MAX1515 features a thermal fault-protection circuit. when the junction temperature rises above +165 c, a thermal sensor shuts down the MAX1515 regardless of v shdn . the MAX1515 is reactivated after the junction temperature cools to +150 c. thermal resistance junction-to-ambient thermal resistance, ja , is highly dependent on the amount of copper area connected to the exposed backside pad. airflow over the board sig- nificantly reduces ja . for heatsinking purposes, evenly distribute the copper area connected at the ic among the high-current pins. refer to the maxim website (www.maxim-ic.com) for qfn thermal considerations. power dissipation power dissipation in the MAX1515 is dominated by conduction losses in the two internal power switches. power dissipation due to supply current in the control section and average current used to charge and dis- charge the gate capacitance of the internal switches (i.e., switching losses?sl) is approximately: psl = c x v in 2 x f sw vv r rr fb ref b ab = + ? ? ? ? ? ? load current inductor current output voltage lx voltage v refin v in v out gnd 0 -2a 0 -2a t off MAX1515 lx gnd fb pgnd v out fbsel1 fbsel0 mode refin ref r b r a c out l figure 4. sink-mode waveforms figure 5. setting v out with a resistive voltage-divider at refin
MAX1515 low-voltage, internal switch, step-down/ddr regulator 18 ______________________________________________________________________________________ where: c = 5nf f sw = switching frequency the combined conduction losses (pcl) in the two power switches are approximated by: pcl = i out 2 x r nmos where: i out = load current r nmos = nmos switch on-resistance design procedure for typical ddr applications, use the recommended component values in table 1. for other applications, use the recommended component values in table 5, or take the following steps: 1) select the desired pwm-mode switching frequency. see figure 6 for maximum operating frequency. 2) select the constant off-time as a function of input voltage, output voltage, and switching frequency. 3) select r toff as a function of off-time. 4) select the inductor as a function of output voltage, off-time, and peak-to-peak inductor current. programming the no-load switching frequency and off-time the MAX1515 features a programmable pwm mode switching frequency, which is set by the input and out- put voltage and the value of r toff . r toff sets the high-side nmos power switch off-time in pwm mode. use the following equation to select the off-time according to the desired no-load switching frequency in pwm mode: where: t off = the programmed off-time v in = the input voltage v out = the output voltage f pwm = no-load switching frequency, pwm mode select r toff according to the formula: v rtoff is typically 1.1v and the recommended values for r toff range from 33.2k to 499k for off-times of 0.35? to 4.5?. frequency variation with output current the operating frequency of the MAX1515 in pwm mode is determined primarily by t off (set by r toff ), v in , and v out as shown in the following formula: where: v chg = the voltage drop in the inductor charge path due to high-side fet r nmos and inductor dcr v dischg = the voltage drop in the inductor discharge path due to low-side fet r nmos and inductor dcr f vv v tv v v pwm in out chg off in chg dischg = + () ?? ? rt s k s toff off = () ? . . 0 035 110 100 t vv fv off in out pwm in = ? 0 200 600 400 800 1000 frequency (khz) maximum recommended operating frequency vs. input voltage v in (v) 1.5 2.5 2.0 3.0 3.5 no load v out = 1.25v v out = 0.9v v out = 2.5v v out = 1.8v v out = 1.5v figure 6. maximum operating frequency vs. input voltage table 5. recommended component values (i out = 3a) v in (v) v out (v) f pwm (khz) l (?) c out (?) r toff (k ) 3.3 2.5 400 1.5 100 49.9 3.3 1.8 400 2.2 150 110 3.3 1.5 480 2.2 180 110 3.3 1.2 420 2.2 220 150 2.5 1.8 430 1.2 100 49.9 2.5 1.5 320 1.8 150 110 2.5 1.2 440 1.5 180 110
MAX1515 low-voltage, internal switch, step-down/ddr regulator ______________________________________________________________________________________ 19 while sourcing current, v chg and v dischg increase with source load current and the voltage across the inductor decreases. this causes the frequency to drop. conversely, while sinking current, v chg and v dischg decrease with sink load current and the voltage across the inductor increases. approximate the change in fre- quency with the following formula: where r drop is the resistance of the internal mosfets (40m typ) and the inductor. inductor selection the key inductor parameters must be specified: induc- tor value (l) and peak current (i peak ). the following equation includes a constant, denoted as lir, which is the ratio of peak-to-peak inductor ac ripple current to maximum dc load current. a higher value of lir allows smaller inductance but results in higher losses and rip- ple. a good compromise between size and losses is found at approximately a 25% ripple-current to load- current ratio (lir = 0.25), which corresponds to a peak inductor current 1.125 times the dc load current: additionally, the minimum inductance chosen must be high enough to limit the inductor current during the high-side switch on-time to less than 1a/?. the peak-inductor current at full load is 1.125 x i out(max) if the above equation is used; otherwise, the peak current is calculated by: choose an inductor with a saturation current at least as high as the peak-inductor current. the inductor select- ed should exhibit low losses at the chosen operating frequency. input capacitor selection the input-filter capacitors reduce peak currents and noise at the voltage source. place a low-esr and low- esl 0.1? capacitor for noise filtering no further than 5mm from in. select the bulk input capacitor according to the rms input ripple-current requirements and volt- age rating: output capacitor selection the output filter capacitor affects the output-voltage ripple, output load-transient response, and feedback- loop stability. for stable operation, the MAX1515 requires a minimum output ripple voltage of v ripple 1% x v out . the minimum esr of the output capacitor is calculated by: stable operation for source-only applications requires the correct output filter capacitor. when choosing the output capacitor, ensure that: for ddr applications, the output capacitance require- ment needs to be two times the above requirement. the output filter capacitor must have low enough equiv- alent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. for applications where the output is subject to violent load transients, the output capacitor? size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in applications without large and fast load transients, the output capacitor? size often depends on how much esr is needed to maintain an acceptable level of out- put voltage ripple. the output ripple voltage of a step- down controller equals the total inductor ripple current multiplied by the output capacitor? esr. therefore, the maximum esr required to meet ripple specifications is: r v i lir esr ripple out max () r v i esr step out max () c vt v fs out refin off out / 105 ? esr l t off % ? 1 ii vvv v rms out max out in out in = ? ? ? ? ? ? ? ? ? () () ii vt l peak out max out off =+ () 2 lv v s a min in max out () () ? 1 1 l vt i lir out off out max = () f ir vt pwm out drop in off = ?
MAX1515 low-voltage, internal switch, step-down/ddr regulator 20 ______________________________________________________________________________________ the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, polymers, and other electrolytics). transient response the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the worst-case output sag can be calculated from: where i out is the maximum load transient. typically, the maximum load transient is equal to the maximum load current ( i out = i load(max) ). for ddr- termination applications, the output must source and sink current. in these applications, the actual peak-to- peak transient current ( i out ) is defined as the sum of both the maximum source and sink load currents: the amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculat- ed as: when using the pulse-skipping source/sink feature (mode = v cc and skip = gnd), the output transient voltage should not exceed or drop below the sink and source (respectively) detection thresholds (v refin ?0mv). applications information dropout operation the MAX1515 improves dropout performance by hav- ing a maximum on-time of 10?. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. keep in mind that transient-response performance of step-down regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the off-time ( i down ) as much as it ramps up during the on-time ( i up ). the ratio h = i up / i down indicates the controller? ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v chg and v dischg are the parasitic voltage drops in the charge and discharge paths (see the frequency variation with output current section), t on(max) is from the electrical characteristics , and t off is the programmed off-time. the absolute minimum input voltage is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, then t off must be reduced or output capacitance added to obtain an acceptable v sag . if operation near dropout is anticipated, calcu- late v sag to be sure of adequate transient response. dropout design example: v out = 2.5v t off = 1? v chg = v dischg = 100mv h = 1.5 = 2.99v dynamic output-voltage transitions by changing the voltage at refin, the MAX1515 can be used in applications that require dynamic output- voltage changes between two set points. an n-channel mosfet can be used to dynamically adjust the second controller? output voltage by changing the resistive vvv svv s in min () .. .(..) =++ + 25 01 15 1 25 01 10 vvv ht v v t in min out chg off out dischg on max () () () =+ + + v il cv soar out out out () 2 2 ii i out source max sink max =+ () () v ilvt lc v v vt lc it c sag out out off out in out out off out out off out + ? () + + () 2 2 2 2
MAX1515 low-voltage, internal switch, step-down/ddr regulator ______________________________________________________________________________________ 21 voltage-divider network at refin. the resulting output voltages are determined by the following equations: forced-pwm operation is required to ensure fast, accu- rate negative voltage transitions when refin is low- ered. since forced-pwm operation disables the zero-crossing comparator, the inductor current can reverse under light loads, quickly discharging the out- put capacitors. for a step voltage change at refin, the rate-of-change of the output voltage is limited by the inductor current ramp, the total output capacitance, the current limit, and the load during the transition. the inductor current ramp is limited by the voltage across the inductor and the inductance. the total output capacitance deter- mines how much current is needed to change the out- put voltage. additional load current slows down the output-voltage change during a positive refin voltage change, and speeds up the output-voltage change dur- ing a negative refin voltage change. increasing the current-limit setting speeds up a positive output-voltage change. to avoid tripping the power-good comparators, the ref- erence-voltage slew rate must be slow enough that the output voltage (v out ) can accurately track the refer- ence voltage (v refin ). add a capacitor across refin and gnd to control the rate-of-change of the refin voltage during dynamic transitions and filter noise. with the additional capacitance, the refin voltage slews between the two set points with a time constant given by r eq x c refin , where r eq is the equivalent parallel resistance seen by the slew capacitor. referring to figure 7, the time constant for a positive refin voltage transition is: and the time constant for a negative refin voltage transition is: pc board layout guidelines good layout is necessary to achieve the intended out- put power level, high efficiency, and low noise. good layout includes the use of a ground plane, careful com- ponent placement, and correct routing of traces using appropriate trace widths. refer to the MAX1515 ev kit for a reference of a good layout. the following points are in order of decreasing impor- tance: 1) minimize switched-current and high-current ground loops. connect the input capacitor? ground, the output capacitor? ground, and pgnd at a single point. connect the resulting island to gnd at only one point. 2) connect the input filter capacitor less than 5mm away from in. the connecting copper trace carries large currents and must be at least 1mm wide, preferably 2.5mm. 3) place the lx node components as close together and as near to the device as possible. this reduces noise, resistive losses, and switching losses. 4) a ground plane is essential for optimal perfor- mance. in most applications, the circuit is located on a multilayer board, and full use of the four or more layers is recommended. use the top and bot- tom layers for interconnections and the inner layers for an uninterrupted ground plane. avoid large ac currents through the ground plane. chip information transistor count: 8258 process: bicmos pos refin rr rr c = + ? ? ? ? ? ? 12 12 pos refin rrr rr r c = + ++ ? ? ? ? ? ? 123 12 3 () vv r rr vv rr rr r out low ref out high ref () () = + ? ? ? ? ? ? = + ++ ? ? ? ? ? ? 2 12 23 12 3 MAX1515 lx gnd fb pgnd v out fbsel1 skip fbsel0 mode refin ref r3 r2 r1 v out(low) v out(high) c out v cc l c refin figure 7. dynamic output voltages
MAX1515 low-voltage, internal switch, step-down/ddr regulator 22 ______________________________________________________________________________________ 18 17 16 15 14 13 123456 7 8 9 10 11 12 24 23 22 21 20 19 MAX1515 thin qfn (4mm x 4mm) top view skip bst lx lx in in + gnd v cc comp fb toff pgood ss refout v dd ic pgnd pgnd fbsel1 fbsel0 mode shdn refin ref pin configuration
MAX1515 low-voltage, internal switch, step-down/ddr regulator ______________________________________________________________________________________ 23 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm
MAX1515 low-voltage, internal switch, step-down/ddr regulator maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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